×
Create a new article
Write your page title here:
We currently have 177 articles on Open Eggbert. Type your article name above or click on one of the titles below and start writing!



Open Eggbert
177Articles
in:

I586 registers: Difference between revisions

No edit summary
No edit summary
Line 26: Line 26:
* Lower and higher halves of the above-mentioned four 16-bit registers can be used as eight 8-bit data registers: AH, AL, BH, BL, CH, CL, DH, and DL.
* Lower and higher halves of the above-mentioned four 16-bit registers can be used as eight 8-bit data registers: AH, AL, BH, BL, CH, CL, DH, and DL.


Regarding the 64-bit processors: There are also four data 64-bit data registers: RAX, RBX, RCX, RDX


Regarding the 32-bit processors: There are also  four data 64-bit data registers: RAX, RBX, RCX, RDX
== Pointer registers ==
There are three data 32-bit pointer registers: EIP, ESP, EBP
 
Their 16-bit equivalent are IP, SP, BP
 
=== Instruction Pointer (EIP) ===
EIP register stores the offset address of the next instruction to be executed. The **IP** in association with the **CS** register (as **CS:IP**) gives the complete address of the current instruction in the code segment.
 
* **CS:IP** is a logical address that points to the current instruction in memory.
* Example:
 
  * If **CS = 0x1000** and **IP = 0x0040**, the logical address of the instruction would be **0x1000:0x0040**, which is the address the CPU will fetch the next instruction from.
 
=== Stack Pointer (SP) ===
The 16-bit **SP** register holds the offset value within the program stack. **SP** in association with the **SS** register (**SS:SP**) refers to the current position of data or address within the program stack.
 
* **SS:SP** provides the complete address within the stack.
* Example:
 
  * If **SS = 0x2000** and **SP = 0x0100**, the full address of the stack data is **0x2000:0x0100**.
 
=== Base Pointer (BP) ===
The 16-bit **BP** register helps in referencing the parameter variables passed to a subroutine. The address in the **SS** register is combined with the offset in **BP** to locate the parameters. **BP** can also be combined with **DI** and **SI** for special addressing.
 
* **SS:BP** points to the base of the current stack frame.
* Example:
 
  * In a function call, **BP** could point to the start of the parameters passed to the function, allowing easy access to them.
  * For example, **BP + 2** might refer to the first argument of a function, while **BP - 4** could refer to a local variable.
 
=== Example Code ===
Here is an example of using the **IP**, **SP**, and **BP** registers:<pre>
push ax          ; Pushes AX onto the stack
mov bp, sp        ; BP now points to the top of the stack (same as SP at this point)
sub sp, 2        ; Adjust SP for local variables (reserve space)
mov [bp-2], 0x1234 ; Store 0x1234 at [BP-2], which is a local variable
</pre>


== External links ==
== External links ==
https://wiki.osdev.org/CPU_Registers_x86
https://wiki.osdev.org/CPU_Registers_x86
[[Category:X86]]
[[Category:X86]]

Revision as of 18:18, 9 November 2024

Types of registers based on the data length

64-bit registers - These do not exist in the i586 instruction set. They exist only in the 64-bit processors. Their names start with the R character.

32-bit registers - Their names start with the E character.

16-bit registers

8-bit registers

Categories of registers

  • General registers
  • Control registers
  • Segment registers

Categories of general registers

  • Data registers
  • Pointer registers
  • Index registers

Data registers

There are four data 32-bit data registers: EAX, EBX, ECX, EDX

  • Lower halves of the 32-bit registers can be used as four 16-bit data registers: AX, BX, CX and DX.
  • Lower and higher halves of the above-mentioned four 16-bit registers can be used as eight 8-bit data registers: AH, AL, BH, BL, CH, CL, DH, and DL.

Regarding the 64-bit processors: There are also four data 64-bit data registers: RAX, RBX, RCX, RDX

Pointer registers

There are three data 32-bit pointer registers: EIP, ESP, EBP

Their 16-bit equivalent are IP, SP, BP

Instruction Pointer (EIP)

EIP register stores the offset address of the next instruction to be executed. The **IP** in association with the **CS** register (as **CS:IP**) gives the complete address of the current instruction in the code segment.

  • **CS:IP** is a logical address that points to the current instruction in memory.
  • Example:
 * If **CS = 0x1000** and **IP = 0x0040**, the logical address of the instruction would be **0x1000:0x0040**, which is the address the CPU will fetch the next instruction from.

Stack Pointer (SP)

The 16-bit **SP** register holds the offset value within the program stack. **SP** in association with the **SS** register (**SS:SP**) refers to the current position of data or address within the program stack.

  • **SS:SP** provides the complete address within the stack.
  • Example:
 * If **SS = 0x2000** and **SP = 0x0100**, the full address of the stack data is **0x2000:0x0100**.

Base Pointer (BP)

The 16-bit **BP** register helps in referencing the parameter variables passed to a subroutine. The address in the **SS** register is combined with the offset in **BP** to locate the parameters. **BP** can also be combined with **DI** and **SI** for special addressing.

  • **SS:BP** points to the base of the current stack frame.
  • Example:
 * In a function call, **BP** could point to the start of the parameters passed to the function, allowing easy access to them.
 * For example, **BP + 2** might refer to the first argument of a function, while **BP - 4** could refer to a local variable.

Example Code

Here is an example of using the **IP**, **SP**, and **BP** registers:

push ax           ; Pushes AX onto the stack
mov bp, sp        ; BP now points to the top of the stack (same as SP at this point)
sub sp, 2         ; Adjust SP for local variables (reserve space)
mov [bp-2], 0x1234 ; Store 0x1234 at [BP-2], which is a local variable

External links

https://wiki.osdev.org/CPU_Registers_x86